Flash memory apparatus and method for merging stored data items

ABSTRACT

A flash memory system is disclosed. The flash memory system includes a flash memory comprising more than one physical block and more than one page, where each page can be in an enabled state, a blank state or a disabled state. In use, a merge control section reads data on an enabled page from a predetermined physical block using a read section, and writes the data onto a blank page using a write section, thereby copying the data on the enabled page onto the blank page. A merge control section then disables the enabled page using a page-disabling section. When the copying of the data from all the enabled pages in the predetermined physical block is finished, the merge control section collectively erases all the data in the physical block using an erase section.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Section 371 of International Application No.PCT/JP02/07456, filed Jul. 23, 2002, the disclosure of which isincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a flash memory system comprising flashmemories and, in particular, a method for merging data items stored ineach of the flash memories.

BACKGROUND ART

A portable information processing device, such as a notebook computer,personal digital assistant (PDA), or digital camera, records largequantities of digital data, such as image data, in an internal recordingmedium. A recording medium that is compact, lightweight and has alarge-recording-capacity is desirable. In particular, a portableinformation processing device, such as a digital video camera (DVC) oran audio player, must record or reproduce large quantities of data froma recording medium in real time. Accordingly, a recording medium thatcan manipulate large quantities of data at a high speed is desirable.

Furthermore, a portable information processing device must operate for along period of time using only an internal power supply such as abattery. Accordingly, a recording medium that reduces power consumptionduring input/output and storing of data is desirable.

In addition, portable information processing devices must exchange dataamong various other information processing devices. For example, imagedata taken with a digital still-video camera (DSC) may be printed usinga printer, subjected to digital processing using a personal computer,transmitted using a cellular phone, or reproduced on a televisionscreen. Accordingly, a recording medium that facilitates the sharing ofdata among the various information processing devices is desirable.

Examples of recording media that meet the above-mentioned requirementsinclude semiconductor memories, flexible disks, hard disks, opticaldisks, and soon. In particular, card-type recording media with built-inflash memories, such as PC cards, (which are hereafter referred to asflash memory cards) are typical. In use, a flash memory card is insertedinto the specific slot of the information processing device andexchanges data with the information processing device. The specific slotarrangement complies with a predetermined standard for flash memorycards. The information processing devices with the specific slots canexchange data with each other through the same flash memory card.

In contrast to a RAM, a flash memory can hold data stored therein for along time without power consumption. Furthermore, a flash memory canelectrically rewrite data in contrast to a ROM. In those respects, aflash memory has advantages as the above-mentioned recording medium overa RAM and a ROM.

A flash memory is generally divided into more than one page each havinga fixed number of memory cells, and further divided into more than onephysical block each having a fixed number of the pages. Each of thememory cells can assume two states, “1” and “0”. Therefore, each one ofthe memory cells can store one-bit data therein. The memory cell of aflash memory, NAND-type flash memory for example, comprises thecharacteristics related to the transition between two states, “1” and“0”. The memory cells in the “1” state can change into the “0” state oneby one. On the other hand, the memory cells in the “0” state can changeinto the “1” state only when all the cells belonging to the samephysical block change collectively. Therefore, data stored in the flashmemory can only be erased collectively in each of the physical blocks.As used above, data is “erased” by initializing of all the memory cellsinside the physical block into the “1” state. On the other hand, datawriting into the flash memory is enabled on the data-erased pages. Asused above, “data writing” means causing some of the memory cells tochange from the “1” state to the “0” state.

The flash memory cannot overwrite data with new data on the same page inwhich data has already been stored. The reason is as follows: in theNAND-type flash memory, for example, the memory cells in the “0” statecannot individually change into the “1” state. Accordingly, overwritingof data with other data on the same page requires prior erasing of datain the whole of the physical block including the page. Accordingly, thetime required for the overwriting of the flash memory is longer thanthat of a RAM, with the difference being the time required for theerasing of the data.

For example, Published Japanese patent application No. H6-301601 gazettediscloses a storage device that achieves high-speed data writing intoflash memories. The storage device writes data into more than one flashmemory or more than one physical block in parallel, thereby shorteningthe writing duration.

FIG. 10 is the block diagram showing an example of data exchange betweena conventional flash memory card 100 and an information processingdevice H (which is hereafter referred to as a host). The flash memorycard 100 is connected with the host H through, for example, 5 types oflines; a data line DAT, a clock line CLK, a power line VDD, a groundline VSS, and a command line CMD.

A host interface 1 receives commands from the host H through the commandline CMD and decodes the commands. When the command is a write command,for example, the host interface 1 decodes the command into a logicaladdress AL provided by the host H as the writing destination of data,and sends the address to the flash memory controller 30. On the otherhand, the host interface 1 receives data objects Da to be written fromthe data line DAT and stores the objects in a buffer 2.

In the flash memory controller 30, an address conversion section 30 a isfed from the host interface 1 with the logical address AL representingthe destination of the data object Da. The address conversion section 30a brings the physical addresses of generally more than one area intocorrespondence with one logical address. Here, one area is equivalentto, for example, two pages inside the cell array 4 b of the flash memory4. In particular, the pages belonging to the same area each belong toseparate physical blocks. The address conversion section 30 a furtherclassifies a plurality of the areas corresponding to the same logicaladdress into three states; blank, enabled, and disabled states.Information about the state of each of the areas is stored in aredundant area added to each of the pages of the flash memory 4. Here,the redundant area consists of a fixed number of the memory cells.Furthermore, the common information about the state of the area isstored in the redundant areas of the pages belonging to the same area.The blank state represents that data has not yet been written in thearea after erasing of data. On the other hand, the enabled and disabledstates are the states of the area in which data is written. The enabledand disabled states represent respectively, that the read section 30 bis allowed to perform reading of data and prohibited from performingreading of data. The address conversion section 30 a, when fed thelogical address AL representing the writing destination of the dataobject Da, selects a blank area in the cell array 4 b and assigns thewrite target area of the data object Da to the blank area. The addressconversion section 30 a further brings the physical address AP of thearea in correspondence with the above-mentioned logical address AL.

A write section 30 c sends the physical address AP of the write targetarea to the address decoder 4 c of the flash memory 4. In conjunctionwith that, the write section 30 c sends the data object Da from thebuffer 2 to the page buffer 4 a of the flash memory 4.

A flash memory 4 comprises, for example, two page buffers 4 a. Each ofthe page buffers 4 a can store one page of data. In other words, the twopage buffers 4 a can store one area of data in total. Accordingly, thedata objects Da to be written, which are sent out from the buffer 2, arestored in the page buffers 4 a on an area-by-area basis. The one-area ofdata items stored in the two page buffers 4 a are written in parallelonto the two pages designated by the address decoder 4 c. Thus, theconventional flash memory card 100 performs the data writing into theflash memory 4 in the two physical blocks in parallel, therebyshortening the writing duration.

The address conversion section 30 a, when fed the logical address ALrepresenting the writing destination of the data object Da, retrievesdata from an enabled area among the physical addresses corresponding tothe logical address AL, together with the above-mentioned operations.When the writing operation ordered by the host is an overwritingoperation, an enabled area generally exists among the areas that havethe physical addresses corresponding to the logical address ALrepresenting the writing destination of the data object Da. At the sametime, a page-disabling section 30 e inside the flash memory controller30 disables the enabled area as described below, thereby prohibiting theread section 30 b from accessing the area. The page-disabling section 30e rewrites the data inside the redundant area corresponding to theenabled page, thereby disabling the page. For example, the sectiondefines the page state as being enabled and disabled when apredetermined bit (which is hereafter referred to as a flag) inside theredundant area is “1” and “0”, respectively. Since the flagcorresponding to the enabled page is “1”, the page-disabling section 30e changes the flag from “1” into “0”. In other words, the section writes“0” into the flag of the redundant area. Thereby disabling the page.

As described above, the conventional flash memory card 100, whenrequested by a host to overwrite data, writes new data in another areawithout erasing original data. Furthermore, the card brings the physicaladdress of the area in which the new data is written into correspondencewith the logical address showing the writing destination. In addition,the card disables the state for the areas in which the original data isstored. Consequently, the read section 30 b, when receiving a readcommand aimed at the logical address from the host, accesses the area inwhich the latest data items are stored among a plurality of the areascorresponding to the logical address. Thus, the overwriting at the samelogical address is realized without erasing of data in the flash memory.Therefore, the overwriting duration is reduced by the erasing duration.

In the conventional flash memory system like the above-described one,each of the overwriting operations at the same logical address entailsthe disabling of the enabled area in which the original data is stored.The result is an increase in the number of the disabled areas.Accordingly, when the overwriting operation is repeated many times atthe same logical address, the number of the disabled areas seriouslyincreases compared with that of the enabled areas. Conventional flashmemory systems capable of managing links between the enabled areasbelonging to the separate physical blocks, fragment data streams such asfiles into areas, and writes the data streams discretely and randomly inblank areas scattered across the various physical blocks. In such aflash memory system, the per-physical-block rate of the disabled areasto the enabled areas is generally high because of the repetition of theoverwriting operation.

In a flash memory, data items are erased only collectively in each ofthe physical blocks. Therefore, the conventional flash memory systemcannot perform data erasing for many disabled areas inside the erasingtarget physical block when the physical block includes even one enabledarea. Accordingly, the ratio of the disabled areas to the enabled areascannot be reduced. As a result, in the conventional flash memory system,the repetition of the overwriting operation seriously reduces the amountof data that can be stored in the flash memory compared with the storagecapacity of the flash memory.

An object of the present invention is to provide a flash memory systemthat reduces the ratio of disabled pages to enabled pages, therebyachieving an increase in the amounts of data that can be stored therein.

BRIEF SUMMARY OF THE INVENTION

Briefly stated the present invention is a flash memory system. Thesystem comprises a flash memory comprising more than one physical blockincluding more than one page having a fixed memory capacity and threestates, namely, blank, enabled, and disabled states; an addressconversion section for converting a logical address entered from theoutside into one of the corresponding physical addresses of the pages; aread section for reading data from the enabled page; a write section forwriting data onto each of the blank pages; an erase section forcollectively erasing data in each of the physical blocks; apage-disabling section for disabling the enabled pages; and a mergecontrol section for selecting a source among the physical blocks, andfor copying data on a predetermined number of the enabled pagesbelonging to the source physical block onto the blank pages using theread and write sections.

Here, the three states of the page are defined as follows. The blankstate represents that data have not yet been written in the page aftererasure of data. On the other hand, the enabled and disabled states arethe states of the page in which data is written. The enabled anddisabled states represent that the read section is allowed to read andprohibited from reading data from the page, respectively.

The above-described flash memory system particularly performs theoverwriting of data at a logical address received from the outside asfollows. At the time of a writing operation, the address conversionsection converts the above-mentioned logical address into the physicaladdress of a blank page. The write section writes new data received fromthe outside onto the page at the physical address. On the other hand,the page-disabling section disables the enabled page on which theoriginal data is stored. Consequently, when reading data from theabove-mentioned logical address, the read section accesses the page inwhich the new data is written in place of the above-mentioned disabledpage. Thus, the above-described flash memory system realizes theoverwriting of data at the same logical address without performingerasure of data. Therefore, the overwriting duration shortens by theduration required to erase data.

Furthermore, in the above-described flash memory system, the mergecontrol section reads data on enabled pages from a predeterminedphysical block using the read section, and writes the data onto separateblank pages using the write section. Consequently, data on enabled pagesinside the predetermined physical block can be copied into otherphysical blocks. In particular, when the data copying is finished on allthe enabled pages inside the predetermined physical block, the erasesection collectively erases data in the physical block. Thereafter, thecopying of data on the enabled pages and the subsequent erasure of datain the physical block are referred to as a merge process. Theabove-described flash memory system can erase data through the mergeprocess on the disabled pages in the physical block that includesenabled pages, in contrast to conventional systems. Accordingly, theabove-described flash memory system can reduce the rate of the disabledpages to the enabled pages. As a result, the amount of data that can bestored when overwriting is repeated is larger than that in theconventional systems.

In one aspect of the invention, when the write section writes new data,the merge control section counts the number of the physical blocksincluding only the blank pages; when obtaining a count equal to orsmaller than a first threshold value, selects the source physical block;selects, as a source page, the enabled page belonging to the sourcephysical block and at least, as many as the pages on which the new datais written; copies data on the source page onto the blank page; disablesthe source page using the page-disabling section; and performs erasingof data using the erase section for the physical block including none ofthe enabled pages.

If the merge process is performed at every time of the writing of newdata, the writing duration is longer by the duration of the mergeprocess than that in the conventional flash memory system. Thus, whennew data is written in the above-described flash memory system, themerge control section counts the number of the physical blocks thatinclude only blank pages (which are hereafter referred to as blankphysical blocks). When the count is smaller than the first thresholdvalue, that is, the area available for the data writing is smaller thana predetermined size, the merge control section performs the mergeprocess. Thus, the above-described flash memory system can reduce theextension of the writing duration due to the merge process by therestriction on the execution timing of the merge process.

Furthermore, the amount of data objects to be written is generally equalto the storage capacity on the order of the integral multiple of thephysical block. Then, the merge control section adjusts the number ofthe source pages to the number equal to or more than the number of thepages on which new data is written. Consequently, when data isoverwritten at the same logical address, the number of the physicalblocks erased through the merge process can be adjusted to theapproximate number of or more than the number of the blank physicalblocks consumed by writing of new data. As a result, the above-describedflash memory system avoids an increase in the ratio of the disabledpages to the enabled pages when the overwriting of data is repeated.

In another aspect, when the write section writes new data, the mergecontrol section counts the number of the physical blocks including onlythe blank pages (namely, the blank physical blocks); when obtaining thecount equal to or smaller than a second threshold value, prohibits thewrite section from writing new data and selects the source physicalblock; copies all data on the enabled pages belonging to the sourcephysical block onto the blank pages belonging to one of the physicalblocks different from the source physical block; and erases the data inthe source physical block using the erase section.

This flash memory system provides the merge process with a higherpriority than the writing operation of new data when the remainingnumber of the physical blocks is smaller than the second thresholdvalue. Consequently, the ratio of the disabled pages to the enabledpages is reduced so that the number of the blank physical blocks isgreater than or equal to the second threshold value. As a result, theabove-described flash memory system may increase the amounts of datathat can be stored.

When the above-described flash memory system performs both theabove-described operation in the case of the remaining number of theblank physical blocks equal to or smaller than the first threshold valueand the above-described operation in the case of the remaining numberequal to or smaller than the second threshold value, the secondthreshold value is smaller than the first threshold value. Consequently,the merge process does not take precedence over the writing operation ofnew data until the blank physical blocks are too small in number toallow the writing of new data therein. As a result, the extension of thewriting duration due to the merge process can be reduced.

The above-described flash memory system may further comprise an addressmemory for storing a list of the addresses of the physical blocks andthe numbers of the disabled pages belonging to the physical blocks. Themerge control section, when selecting the source physical block,accesses the address memory and consults the above-mentioned list.Thereby, the section can select the source physical blocks easily andquickly in decreasing order of the number of the disabled pages that thephysical blocks include. As a result, the time required to theabove-described merge process can shorten since the number of theenabled pages whose data should be copied is minimized.

In an additional aspect, wherein a predetermined number of the pagesbelonging to each of the separate physical blocks are assigned to onearea; the read section reads data from more than one of the enabledpages belonging to the same area in parallel; the write section writesdata onto more than one of the blank pages belonging to the same area inparallel; and the page-disabling section disables all of the enabledpages belonging to the same area.

This flash memory system always performs input and output of data to andfrom the flash memory on an area-by-area basis, that is, more than onepage in parallel. Accordingly, the system operates at speeds faster thanthat of the flash memory systems performing input and output of data toand from the flash memory on a page-by-page basis.

In a further aspect, wherein the flash memory system comprises two ormore of the flash memories; and at least two of the read section, thewrite section, the erase section, the page-disabling section, and themerge control section operate in parallel with each other for therespective flash memories.

In this flash memory system, for example, the write section writes newdata in one of the flash memories. In parallel with that, the mergecontrol section performs the merge process in another of the flashmemories. Consequently, the extension of the writing duration due to themerge process can be reduced compared to that of the flash memory systemthat includes only one flash memory.

In another aspect, a method for merging data items stored in a flashmemory is the method for merging data items stored in the flash memorycomprising more than one physical block including more than one pagehaving a fixed memory capacity and three states, namely, blank, enabled,and disabled states, and comprises the steps of selecting a source amongthe physical blocks; copying data on a predetermined number of theenabled pages belonging to the source physical block onto the blankpages; and erasing data in each of the physical blocks.

This method for merging copies data on the enabled pages inside apredetermined physical block into another physical block and erases datain the physical block collectively. Through such a merge process, dataon the disabled pages of the physical blocks, including enabled pages,can be erased. Therefore, the above-described method for merging canreduce the ratio of the disabled pages to the enabled pages. As aresult, the amounts of data that can be stored in the flash memory canincrease.

Another aspect of the present invention is the method for merging dataitems stored in the flash memory comprising more than one physical blockincluding more than one page having a fixed memory capacity and threestates, namely, blank, enabled, and disabled states, and comprises thesteps of: counting the number of the physical blocks including only theblank pages; comparing the count with a first threshold value;performing writing of new data and obtaining the number of the targetpages of the writing when the count is equal to or smaller than thefirst threshold value; selecting a source among the physical blocks;selecting, as a source page, the enabled page (a) belonging to thesource physical block, and (b) at least, as many as the pages on whichthe new data is written; copying data on the source page onto the blankpage; disabling the source page; selecting the physical block includingnone of the enabled pages as an erasing target physical block; anderasing data in the erasing target physical block.

This method for merging performs the merge process when the number ofthe blank physical blocks is smaller than the first threshold value, inother words, when the area available for the data writing is smallerthan a predetermined size. Accordingly, the restriction on the executiontiming of the merge process can reduce the extension of the writingduration due to the merge process.

Furthermore, the amount of data objects to be written is generally equalto the storage capacity on the order of the integral multiple of thephysical block. In the above-described method for merging, the number ofthe source pages is equal to or more than the number of the target pagesof writing of new data. Accordingly, the physical blocks that becomeerasable by the copy of the data on the enabled pages can increase innumber to the order of or more than the number of the blank physicalblocks consumed by the writing of new data, especially when data isoverwritten at the same logical address. As a result, theabove-described method for merging can avoid the increase in the rate ofthe disabled pages to the enabled pages when the overwriting of data isrepeated.

According to still another aspect of the present invention is the methodfor merging data items stored in the flash memory comprising more thanone physical block including more than one page having a fixed memorycapacity and three states, namely, blank, enabled, and disabled states,comprises the steps of: counting the number of the physical blocksincluding only the blank pages (namely, the blank physical blocks);comparing the count with a second threshold value; prohibiting writingof new data when the count is equal to or smaller than the secondthreshold value; selecting a source among the physical blocks;selecting, as source pages, all data items on the enabled pagesbelonging to the source physical block; copying the data item on thesource page onto the blank page belonging to the physical blockdifferent from the source physical block; and erasing data in the sourcephysical block.

This method for merging provides the merge process with a higherpriority than the writing operation of new data when the remainingnumber of the blank physical blocks is smaller than the second thresholdvalue. Consequently, the ratio of the disabled pages to the enabledpages is reduced so that the number of the blank physical blocks isapproximately equal to or greater than the second threshold value. As aresult, the amounts of data that can be stored in the flash memory canincrease in the above-described method for merging.

When the above-described method for merging includes both theabove-described merge process in the case of the remaining number of theblank physical blocks equal to or smaller than the first threshold valueand the above-described merge process in the case of the remainingnumber equal to or smaller than the second threshold value, the secondthreshold value is smaller than the first threshold value. Consequently,the merge process does not take precedence over the writing operation ofnew data until the blank physical blocks are too small in number toallow the writing of new data therein. As a result, the extension of thewriting duration due to the merge process can be reduced.

In the above-described method for merging, the step of selecting thesource physical block may comprise the substep of consulting a list ofthe addresses of the physical blocks and the numbers of the disabledpages that belong to the physical blocks. Consequently, the sourcephysical block can be selected easily and quickly in decreasing order ofthe number of the disabled pages that the physical blocks include. As aresult, the time required to the above-described merge process canshorten since the number of the enabled pages whose data should becopied is minimized.

While the novel features of the invention are set forth particularly inthe appended claims, the invention, both as to organization and content,will be better understood and appreciated, along with other objects andfeatures thereof, from the following detailed description taken inconjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing data exchanges between a flash memorycard 10 according to Embodiment 1 of the present invention and a host H;

FIG. 2 is a schematic diagram showing the structure of a cell array 4 binside a flash memory 4 according to Embodiment 1 of the presentinvention;

FIG. 3 is a flow chart about operations of a merge control section 3 faccording to Embodiment 1 of the present invention;

FIG. 4 is a flow chart about the first merge process S3, one of theoperations of the merge control section 3 f according to Embodiment 1 ofthe present invention;

FIG. 5 is a schematic diagram showing changes in the states of the pagesinside the flash memory 4 during the first merge process S3 according toEmbodiment 1 of the present invention;

FIG. 6 is a flow chart about the second merge process S4, another of theoperations of the merge control section 3 f according to Embodiment 1 ofthe present invention;

FIG. 7 is a schematic diagram showing changes in the states of the pagesinside the flash memory 4 during the second merge process S4 accordingto Embodiment 1 of the present invention;

FIG. 8 is a block diagram showing data exchanges between a flash memorycard 10A according to Embodiment 2 of the present invention and a hostH;

FIG. 9 is a block diagram showing data exchanges between a flash memorycard 10B according to Embodiment 3 of the present invention and a hostH;

FIG. 10 is a block diagram showing an example of data exchanges betweena conventional flash memory card 100 and a host H.

It will be recognized that some or all of the Figures are schematicrepresentations for purposes of illustration and do not necessarilydepict the actual relative sizes or locations of the elements shown.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following explains the best mode for carrying out the presentinvention by describing some preferable Embodiments and referring to thedrawings.

Embodiment 1

FIG. 1 is a block diagram showing data exchanges between a flash memorycard 10 according to Embodiment 1 of the present invention and a host H.The flash memory card 10 is connected with the host H through thefollowing five types of lines. The lines are composed of nine lines intotal; four data lines DAT0–3, a clock line CLK, a power line VDD, twoground lines VSS1 and VSS2, and a command line CMD.

A host interface 1 is the circuit for performing communications directlywith the host H through the above-mentioned nine lines. The hostinterface 1 receives commands from the host H through the command lineCMD and decodes the commands. After that, the host interface performs,for example, the following operations in response to the commands. Whena command from the host H is a read command, the host interface 1decodes the command into the logical address AL of the read target andsends the address to a flash memory controller 3. When a command fromthe host H is a write command, the host interface 1 decodes the commandinto the logical address AL of the write target and sends the address tothe flash memory controller 3. On the other hand, the host interface 1reads data objects to be written from the data lines DAT0–3 insynchronization with a transfer clock received from the clock line CLK,and stores the data objects in the buffer 2. When a command from thehost H is an erase command, the host interface 1 decodes the commandinto the logical address AL of the erase target and sends the address tothe flash memory controller 3.

Preferably the buffer 2 is an SRAM. and the buffer 2 temporarily storesthe data objects Da exchanged between the host interface 1 and the flashmemory controller 3. Consequently, the host interface 1 and the flashmemory controller 3 can exchange data objects Da with each other withoutbeing obstructed by a difference in operating speeds, that is, adifference in frequency between the transfer clock CLK from the host Hand the internal clock of the flash memory card 10. In addition, thebuffer 2 provides the host interface 1 and the flash memory controller 3with respective working memory spaces.

Flash memories 4 are NAND-type EEPROM (electrically erasableprogrammable ROM) preferably, and include a page buffer 4 a, a cellarray 4 b, an address decoder 4 c, and an erasing circuit 4 d.

FIG. 2 is a schematic diagram showing the structure of the cell array 4b. The cell array 4 b is an assembly of a plurality of the physicalblocks B0, B1, B2, etc. Each of the physical blocks has the followingtwo-dimensional arrangement of many memory cells: eight memory cellsconnected in the NAND type compose one line and 512 lines compose onepage. Furthermore, a redundant area composed of 16 lines is added toevery one page. The arrangement of one page with the addition of theredundant area composes one unit, and 32 units compose one physicalblock. For example, the first physical block B0 includes 32 pagesP0–P31. The redundant areas Pr0–Pr31 of 16 bytes each are added to therespective pages P0–P31. Similarly, the second physical block B1includes 32 pages Q0–Q31, and the redundant areas Qr0–Qr31 are added tothe respective pages Q0–Q31. Likewise other of the physical blocks B2,B3, etc.

Since one memory cell stores one bit data, in the cell array 4 b, 8bits=1 byte are stored per one line, 512 bytes per one page, and 512bytes×32=16 KB per one physical block. Furthermore, in Embodiment 1, thecell array 4 b comprises 210=1024 of the physical blocks, thuscomprising the storage capacity of 16 KB×1024=16 MB.

The flash memory 4 comprises, for example, two page buffers 4 a. Each ofthe page buffers 4 a can store one-page data. When data is written intothe cell array 4 b, data items Da from the flash memory controller 3, ingroups of 2×512 bytes, are temporarily stored in the two page buffers 4a. Furthermore, the data items are written in parallel from therespective page buffers 4 a onto two separate pages in the cell array 4b. When data is read from the cell array 4 b, data items are read inparallel from two separate pages inside the cell array 4 b, andtemporarily stored in the two respective page buffers 4 a. Furthermore,the data items are transferred in parallel from the two page buffers 4 ato the flash memory controller 3 as a series of data Da.

Two target pages of writing or reading are selected from separatephysical blocks. For example, the two pages shown hatched in FIG. 2,that is, the first pages P0 and Q0 of the first physical block B0 andthe second physical block B1, respectively, are selected. Similarly,from one of the odd-numbered physical blocks and one of theeven-numbered physical blocks, the respective pages at correspondingpositions are selected. At that time, the address decoder 4 c performsthe selection according to the physical address AP received from theflash memory controller 3. The two-page pair inside the cell array 4 bselected in such a manner is hereafter referred to as one area.

The erasing circuit 4 d applies a high voltage across the physical blockcorresponding to the physical address AP received from the flash memorycontroller 3, thereby collectively erasing data stored inside thephysical block. In order to perform the data erasing separately in eachof the physical blocks at that time, the physical blocks inside the cellarray 4 b are electrically insulated from each other.

The flash memory controller 3 performs data input/output control overthe flash memory 4 using the components described as follows.

An address conversion section 3 a receives a logical address AL from thehost interface 1. Furthermore, the section selects the areacorresponding to the logical address AL from the inside of the cellarray 4 b of the flash memory 4, and converts the logical address ALinto the physical address AP of the area. Generally, the addressconversion section 3 a assigns more than one physical address AP of areato one logical address AL. Furthermore, the section classifies aplurality of the areas corresponding to the same logical address AL intothree states, namely, blank, enabled, and disabled states, and selectsthe physical addresses AP of the areas according to the respectivestates.

The blank state represents that data has not yet been written in thearea after the erasure of data. On the other hand, the enabled anddisabled states are the states of the area in which data is written. Theenabled and disabled states represent that the read section 3 b isallowed to read and prohibited from reading data from the area,respectively.

Information about the state of each area is stored in the redundant areaadded to each page of the flash memory 4 (such as the redundant area Pr0corresponding to the page P0). In particular, the common informationabout the state of the area is stored in the redundant areas of thepages belonging to the same area.

The address conversion section 3, at startup of the flash memory card10, checks the states of all the areas inside the cell array 4 b of theflash memory 4. Furthermore, the address conversion section 3 creates,inside the buffer 2, a table 2 a regarding the state of each of theareas (which is hereafter referred to as a state table). The state table2 a is, for example, a list of the physical addresses of areas, thelogical addresses corresponding to the areas, and the information aboutthe states of the areas.

When a logical address AL shows a target of reading data, the addressconversion section 3 a consults the state table 2 a, thereby selectingan enabled area from among the areas inside the cell array 4 bcorresponding to the logical address AL. The read section 3 b sends thephysical address AP of the enabled area to the flash memory 4. Theaddress decoder 4 c decodes the physical address AP entered into theflash memory 4. Consequently, data items are read in parallel from therespective pages belonging to the area inside the cell array 4 bcorresponding to the physical address AP into the two page buffers 4 a.The read section 3 b transfers the data items Da from the page buffers 4a to the buffer 2.

When a logical address AL shows a target of writing data, the addressconversion section 3 a consults the state table 2 a, thereby selectingblank areas from the inside of the cell array 4 b. Furthermore, theaddress conversion section 3 a assigns the physical addresses AP of theblank areas to the logical address AL of the write target. The writesection 3 c transfers the data objects Da to be written, in groups of2×512 bytes, from the buffer 2 to the page buffers 4 a inside the flashmemory 4. In conjunction with that, the section sends the physicaladdress AP of the blank area selected by the address conversion section3 a to the flash memory 4. The address decoder 4 c decodes the physicaladdress AP entered in the flash memory 4. Consequently, data items arewritten in parallel from the different page buffers 4 a onto therespective pages belonging to the area inside the cell array 4 bcorresponding to the physical address AP. Furthermore, at the end of thedata writing, the address conversion section 3 updates the state table 2a and rewrites the item regarding the state of the write target areafrom “blank” to “enabled”.

As described above, the writing and reading of data into and from theflash memory 4 are performed through the two page buffers 4 a on anarea-by-area basis, that is, one page each of the two separate physicalblocks in parallel. Thus, the flash memory card 10 according toEmbodiment 1 shortens the writing and reading durations for the flashmemory 4.

When a logical address AL shows a target of erasing data, the addressconversion section 3 a identifies the physical address AP of thephysical block corresponding to the logical address AL. An erase section3 d sends the physical address AP of the erasing target identified bythe address conversion section 3 a to the erasing circuit 4 d inside theflash memory 4. The erasing circuit 4 d stops the address decoder 4 c,and applies a predetermined high voltage across the physical blockcorresponding to the received physical address AP, thereby performingthe erasing of data for the physical block. Furthermore, at the end ofthe data erasing, the address conversion section 3 updates the statetable 2 a and rewrites “enabled” into the items regarding the states ofall the areas inside the physical block of the erasing target.

At the time of the data writing, the address conversion section 3 aconsults the state table 2 a along with the above-described operations,and retrieves an enabled area among the areas of the physical addressescorresponding to the logical address AL of the write target. When thewriting requested by the host H is the overwriting of data, generally anenabled area exists in the areas of the physical addresses correspondingto the logical address AL. Then, a page-disabling section 3 e disablesthe enabled area as described below. Furthermore, the address conversionsection 3 updates the state table 2 a, and rewrites the item regardingthe state of the area from “enabled” to “disabled.” Consequently, theread section 3 b is prohibited from accessing to the area.

The page-disabling section 3 e rewrites data inside the redundant areacorresponding to the enabled page, thereby disabling the page. Forexample, it is defined that a page is enabled and disabled when thepredetermined one bit (flag) inside the redundant area is “1” and “0,”respectively. Since the flag corresponding to the enabled page is “1,”the page-disabling section 3 e changes the flag from “1” to “0,” inother words, writes “0” into the flag inside the redundant area, therebydisabling the page.

As described above, the flash memory card 10 according to Embodiment 1,when requested the overwriting of data by the host H, writes new data inanother area without erasing the original data. Furthermore, the cardassigns the physical address of the area in which the new data iswritten to the logical address of the write target. In addition, thecard disables states of the areas at the other physical addressescorresponding to the logical address. Consequently, when receiving fromthe host a read command aimed at the logical address, the read section 3b can access only the area storing the latest data items among aplurality of the areas corresponding to the logical address. Thus, theoverwriting of data at the same logical address is realized withoutentailing an erasure of data in the flash memory 4. Therefore, theoverwriting duration shortens by the erasing duration.

The flash memory card 10 according to Embodiment 1 further comprises amerge control section 3 f inside the flash memory controller 3. Asdescribed above, the overwriting of data produces disabled pages.Accordingly, the ratio of the disabled areas to the enabled areasincreases when the overwriting of data is repeated. The merge controlsection 3 f controls the read section 3 b, the write section 3 c, theerase section 3 d, and the page-disabling section 3 e as follows,thereby copying data on the enabled pages inside a predeterminedphysical block onto the blank pages inside other physical blocks.Furthermore, the merge control section erases the original data in thephysical block, thereby increasing the number of the physical blocksincluding only blank pages (the blank physical blocks). As a result, theratio of the disabled areas to the enabled areas can be reduced.

FIG. 3 is a flow chart showing the operation of the merge controlsection 3 f.

The merge control section 3 f starts up at the time of writing of datainto the flash memory 4.

Step S1:

The merge control section 3 f consults the state table 2 a inside thebuffer 2 and counts the number N of the blank physical blocks.

Step S2:

The number N of the blank physical blocks counted in Step S1 is comparedwith each of the first threshold value th1 and the second thresholdvalue th2. Here, the first threshold value th1 and the second thresholdvalue th2 are, for example, equal to about 50% and about 20% of thenumber of all the physical blocks inside the cell array 4 b,respectively. Furthermore, the merge control section 3 f causes theprocess to branch as follows, depending on the result of comparison. (1)The merge control section 3 f stops when the number N of the blankphysical blocks is equal to or more than the first threshold value th1(N≧=th1). (2) The merge control section 3 f performs the first mergeprocess S3 when the number N of the blank physical blocks is smallerthan the first threshold value th1 and equal to or more than the secondthreshold value th2 (th2≦N<th1). (3) The merge control section 3 fperforms the second merge process S4 when the number N of the blankphysical blocks is smaller than the second threshold value th2 (N<th2).

Through Step S1 and Step S2, the merge control section 3 f performs thefollowing merge process only when the number N of the blank physicalblocks is smaller than the first threshold value th1, in other words,only when the remaining area available for the data writing is small.Thus, the flash memory card 10 according to Embodiment 1 limits theextension of the writing duration due to the merge process.

<The First Merge Process S3>

FIG. 4 is a flow chart showing the first merge process S3. FIG. 5 is aschematic diagram showing changes in the states of the pages inside thecell array 4 b during the first merge process S3. In Embodiment 1, thecorresponding pages in one of the odd-numbered physical blocks and oneof the even-numbered physical blocks belong to the same area.Furthermore, the data input/output operations are performed area by areain parallel. Accordingly, the changes in states of pages aresubstantially common between the odd-numbered physical blocks and theeven-numbered physical blocks. Therefore, FIG. 5 shows only theodd-numbered physical blocks inside the cell array 4 b.

FIG. 5 represents the data items stored in the respective areas P0, P1,P2, etc. as the reference symbols D0, D1, D2, etc. written inside theboxes showing the respective areas. In addition, the states of the areasare represented as the numerals 1 and 0 written inside the boxes showingthe corresponding redundant areas Pr0, Pr1, Pr2, etc. Here, the numerals1 and 0 show the enabled and disabled states, respectively. Furthermore,the states of the areas are blank when the boxes showing the areas areblank.

Substep S31:

As shown in (a) of FIG. 5, new data items (for example, d1, d2, and d3)are written into the blank areas. Then, the merge control section 3 fobtains the number k (for example, 3) of the blank areas in which thenew data items are written.

Substep S32:

The merge control section 3 f consults an address table 2 b inside thebuffer 2, and selects the physical block BL as a source of copying indecreasing order of the number of the disabled areas, the physical blockincluding the largest number of the disabled areas first. Here, theaddress table 2 b is a list of the addresses of the physical blocks andthe numbers of the disabled pages belonging to the physical blocks. Forexample, the top physical block BL is selected as the source physicalblock in (a) of FIG. 5.

Substep S33:

The merge control section 3 f consults the state table 2 a inside thebuffer 2, and selects the same number of the enabled areas of the sourcephysical block BL as the number of the areas obtained in Substep S31,that is, k areas in order, the top area P0 first. For example, the threeenabled areas P0, P1, and P3 are selected in (a) of FIG. 5. Here, whenthe number of the enabled areas inside the source physical block BL issmaller than k, Substep S32 is performed again, and thereby selectinganother physical block as a source physical block and the rest of theenabled areas are selected from the physical block.

Substep S34:

The merge control section 3 f consults the state table 2 a inside thebuffer 2 and selects the same number of blank areas as the number of theareas obtained in Substep S31, that is, k areas from a physical blockdifferent from the source physical block BL. For example, the threeblank areas CP0, CP1, and CP3 are selected in (a) of FIG. 5.

Substep S35:

The merge control section 3 f reads data items from the enabled areasselected in Substep S33 using the read section 3 b. The data items readare temporarily stored in the buffer 2. Furthermore, the merge controlsection 3 f writes the data items temporarily stored in the buffer 2into the respective blank areas selected in Substep S34 using the writesection 3 c. Thus, data items on the k enabled areas inside the sourcephysical block BL are copied into the respective blank areas of theother physical blocks. For example, the data items D0, D1, and D3 in thethree enabled areas P0, P1, and P3 inside the source physical block BLare copied into the three blank areas CP0, CP1, and CP3, respectively,in (a) of FIG. 5.

Substep S36:

The merge control section 3 f disables the k enabled areas inside thesource physical block BL using the page-disabling section 3 e. In (b) ofFIG. 5, for example, data in the redundant areas Pr0, Pr1, and Pr3corresponding to the three enabled areas P0, P1, and P3 inside thesource physical block BL is changed from “1” to “0.” Furthermore, themerge control section 3 f updates the state table 2 a inside the buffer2, and rewrites the items regarding the states of the k enabled areasinside the source physical block BL from “enabled” to “disabled.” Inconjunction with that, the merge control section 3 f updates the addresstable 2 b inside the buffer 2 based on the state table 2 a updated.

Substep S37:

The merge control section 3 f consults the state table 2 a inside thebuffer 2 and selects the physical block including only disabled areas,or alternatively, only a large number of disabled areas and a smallnumber of blank areas, and assigns the physical block as an erasingtarget physical block BE. In (c) of FIG. 5, for example, the topphysical block BE is selected as an erasing target since the states ofall the areas inside the physical block BE are disabled.

Substep S38:

It is checked whether an erasing target physical block BE can beselected in Substep S37. The merge control section 3 f causes theprocess to branch to Substep S39 when an erasing target physical blockBE exists, and finishes the first merge process S3 at other times.

Substep S39:

The merge control section 3 f performs the erasing of data for theerasing target physical block BE using the erase section 3 d. In (d) ofFIG. 5, for example, all the boxes showing the areas inside the erasingtarget physical block BE are drawn as blank boxes so as to representthat the states of all the areas are changed into blank states. Afterthe end of the data erasing, the merge control section 3 f updates thestate table 2 a inside the buffer 2, and rewrites “enabled” into theitems regarding the states of all the areas of the erasing targetphysical block BE. In conjunction with that, the merge control section 3f updates the address table 2 b inside the buffer 2 based on the updatedstate table 2 a. Then, the merge control section 3 f repeats the processfrom Substep S37.

As described above, the first merge process S3 is performed at each timeof the data writing when the number N of the blank physical blocks issmaller than the first threshold value th1. Generally the amounts of thedata objects to be written are equal to the storage capacity to be onthe order of the integral multiple of the physical block. On the otherhand, in Substep S33, the merge control section 3 f selects as manyenabled areas as the areas in which new data is written. Accordingly,generally the number of physical blocks that become erasable through thefirst merge process S3 can be adjusted to be on the order of the numberof the blank physical blocks consumed by the writing of new data,especially when data is overwritten into the same logical address. As aresult, the flash memory card 10 according to Embodiment 1 can suppressan increase in the ratio of the disabled areas to the enabled areas atthe time of the repetition of the overwriting of data.

<The Second Merge Process S4>

FIG. 6 is a flow chart showing the second merge process S4. FIG. 7 is aschematic diagram showing changes in the states of the pages inside thecell array 4 b during the second merge process S4. FIG. 7 shows only theodd-numbered physical blocks inside the cell array 4 b in a mannersimilar to FIG. 5. Furthermore, data items stored in the areas and thestates of the areas are shown as reference symbols similar to thoseshown in FIG. 5.

Substep S41:

The merge control section 3 f prohibits the write section 3 c fromwriting new data in contrast to the time of the first merge process S3.

Substep S42:

The merge control section 3 f consults the address table 2 b inside thebuffer 2 and selects the source physical block BL. The blocks areselected in decreasing order of the number of the disabled areas, withthe physical block including the largest number of the disabled areasfirst, in a manner similar to Substep S32 of the first merge process S3.In (a) of FIG. 7, for example, the top physical block BL is selected asthe source physical block.

Substep S43:

The merge control section 3 f consults the state table 2 a inside thebuffer 2 and selects all the enabled areas inside the source physicalblock BL. In (a) of FIG. 7, for example, all the enabled areas P0 and P3inside the physical block BL are selected.

Substep S44:

The merge control section 3 f consults the state table 2 a inside thebuffer 2 and selects the same number of blank areas as the number ofenabled areas selected in Substep S43 and from a physical blockdifferent from the source physical block BL. In (a) of FIG. 7, forexample, the top two areas CP0 and CP1 inside the one Bn of the blankphysical blocks are selected.

Substep S45:

The merge control section 3 f reads data items from the enabled areasselected in Substep S43 using the read section 3 b. The data items readare temporarily stored in the buffer 2. Furthermore, the merge controlsection 3 f writes the data items temporarily stored in the buffer 2into the respective blank areas selected in Substep S44 using the writesection 3 c. Thus, the data items in all the enabled areas inside thesource physical block BL are copied into the respective blank areas ofanother physical block. In (a) of FIG. 7, for example, the data items D0and D3 in the enabled areas P0 and P3 inside the source physical blockBL are copied into the two blank areas CP0 and CP1 of the blank physicalblock Bn, respectively.

Substep S46:

The merge control section 3 f selects the source physical block BL as anerasing target physical block BE as shown in (b) of FIG. 7. Furthermore,the merge control section performs the erasing of data for the erasingtarget physical block BE using the erase section 3 d. In (c) of FIG. 7,for example, all the boxes showing the areas inside the erasing targetphysical block BE are drawn as blank boxes so as to represent that thestates of all the areas are changed into blank states. After the end ofthe data erasing, the merge control section 3 f updates the state table2 a inside the buffer 2 and rewrites “enabled” into the items regardingthe states of all the areas inside the erasing target physical block BE.In conjunction with that, the merge control section 3 f updates theaddress table 2 b inside the buffer 2 based on the state table 2 aupdated.

As described above, the second merge process S4 is performed when thenumber N of the blank physical blocks is smaller than the secondthreshold value th2. At that time, the writing of new data isprohibited, and the producing of an increase in the number N of theblank physical blocks through Substeps S42–S46 is placed at a higherpriority. Consequently, the ratio of the disabled areas to the enabledareas is reduced so that the number N of the blank physical blocks issecured at or beyond the second threshold value th2. As a result, theflash memory card 10 according to Embodiment 1 increases the amounts ofdata that can be stored therein.

The flash memory 4 comprises the two page buffers 4 a in Embodiment 1.Alternatively, the flash memory may comprise only one page buffer, orthree or more of the page buffers.

Embodiment 2

FIG. 8 is a block diagram showing data exchanges between a flash memorycard 10A according to Embodiment 2 of the present invention and a hostH. The flash memory card 10A according to Embodiment 2 comprises twoflash memories in contrast to the counterpart 10 of Embodiment 1 (FIG.1). In FIG. 8, components similar to those of Embodiment 1 are markedwith the same reference symbols as those of Embodiment 1. Furthermore,the description of Embodiment 1 is cited regarding those similarcomponents.

A flash memory controller 3A and two flash memories 4A and 4B accordingto Embodiment 2 are really similar in internal structure to theirrespective counterparts 3 and 4 of Embodiment 1, and therefore FIG. 1 iscited regarding them.

The duration of data transfer between the flash memory controller 3A andthe flash memory 4A or 4B inside the page buffers 4 a is on the order ofseveral tens of nsec. On the other hand, the duration of writing datafrom the page buffer 4 a into the cell array 4 b is on the order ofseveral hundreds of nsec. Using the difference between those processingtimes, the flash memory controller 3A according to Embodiment 2 performsa writing operation of data into one of the flash memories and a mergeprocess in the other of the flash memories in parallel as describedbelow. Consequently, the extension of the writing duration due to themerge process can be reduced compared with that of the flash memory card10 according to Embodiment 1.

For example, when writing data into the first flash memory 4A, a writesection 3 c inside the flash memory controller 3A transfers the dataobject Da to be written into the first flash memory 4A area by area, ina manner similar to that of Embodiment 1. The merge control section 3 finside the flash memory controller 3A, at every time of the transfer ofthe one area, starts up and performs Step S1 and Step S2 for the secondflash memory 4B in a manner similar to that of Embodiment 1. The mergecontrol section 3 f further performs the first merge process S3 or thesecond merge process S4 according to the result of the comparison inStep S2, in a manner similar to that of Embodiment 1.

<The First Merge Process S3>

In the first merge process S3 according to Embodiment 2, in contrast tothat of Embodiment 1, the merge control section 3 f obtains in SubstepS31 the number of the areas in which new data is written inside thefirst flash memory 4A. In Substep S33, enabled as many areas as theareas in which new data is written inside the first flash memory 4A areselected from the source physical block inside the second flash memory4B. Consequently, one area of the second flash memory 4B is copied intoanother area in parallel with the writing of data in one area into thefirst flash memory 4A. Furthermore, the number of the target areas ofthe first merge process S3 in the second flash memory 4B is equal to thenumber of the write target areas in the first flash memory 4A.Accordingly, the duration required of the first merge process S3 in thesecond flash memory 4B is nearly equal to the writing duration in thefirst flash memory 4A. As a result of the above-described operations,the extension of the writing duration due to the first merge process S3can be reduced in Embodiment 2, compared with that in Embodiment 1.

<The Second Merge Process S4>

In the second merge process S4 according to Embodiment 2, in contrast tothat of Embodiment 1, the merge control section 3 f allows the datawriting into the first flash memory 4A. Consequently, the data writinginto the first flash memory 4A can be performed in parallel with thesecond merge process S4 in the second flash memory 4B. Therefore, theextension of the writing duration due to the second merge process S4 canbe reduced in Embodiment 2, compared with that in Embodiment 1.

Embodiment 3

FIG. 9 is a block diagram showing data exchanges between a flash memorycard 10B according to Embodiment 3 of the present invention and a hostH. The flash memory card 10B according to Embodiment 3 comprises twoflash memories in a manner similar to the counterpart 10A of Embodiment2 (FIG. 8). In FIG. 9, components similar to those of Embodiment 1 aremarked with the same reference symbols as those of Embodiment 1.Furthermore, the description of Embodiment 1 is cited regarding thosesimilar components.

The two flash memories 4A and 4B according to Embodiment 3 are reallysimilar in internal structure to their counterpart 4 of Embodiment 1,and therefore FIG. 1 is cited regarding them.

A flash memory controller 3B according to Embodiment 3 includes twointernal structures, each of which is similar to that of its counterpart3 according to Embodiment 1. Of the internal structures similar to thatof the flash memory controller 3 according to Embodiment 1, one isconnected to the first flash memory 4A, and the other is separatelyconnected to the second flash memory 4B. Furthermore, the internalstructures are separately connected to the buffer 2B through theseparate data buses. Because of such composition, the flash memory card10B according to Embodiment 3 can perform the writing operation and themerge process in parallel for the two flash memories 4A and 4B in amanner similar to that of Embodiment 2. In contrast to Embodiment 2, inparticular, data transmissions between the buffer 2B and the flashmemory controller 3B and data transmissions between the flash memorycontroller 3B and the flash memories 4A and 4B are also performed inparallel. Accordingly, the writing duration can be further decreased bythe data transfer duration compared with that of Embodiment 2.

As described above, the flash memory system according to the presentinvention can copy data on the enabled pages inside a predeterminedphysical block into other physical blocks. Furthermore, at the end ofthe copying of data on all the enabled pages inside the predeterminedphysical block, the system can collectively erase data in the physicalblock. Through such a merge process, the flash memory system accordingto the present invention can erase data on the disabled pages inside thephysical block including enabled pages, in contrast to conventionalsystems. Accordingly, the flash memory system according to the presentinvention can reduce the rate of the disabled pages to the enabledpages. As a result, the amount of data that can be stored at the time ofthe repetition of the overwriting of data is larger than that of theconventional systems.

The flash memory system according to the present invention may furtherperform the above-described merge process when new data is writtentherein and the number of blank physical blocks is smaller than thefirst threshold value. Thus, the above-described flash memory system canreduce the extension of the writing duration due to the copying of databy the restriction of the execution timing of the merge process.

The flash memory system according to the present invention may adjustthe number of the source pages to be equal to or more than the number ofthe pages on which new data is written. Consequently, when data isoverwritten at the same logical address, the system can adjust thenumber of the physical blocks erased in the above-described mergeprocess to be greater than or equal to the number of blank physicalblocks consumed by the writing of new data. As a result, the system canavoid an increase in the ratio of the disabled pages to the enabledpages at the time of the repetition of the overwriting of data.Therefore, the system can increase the amounts of data that can bestored.

The flash memory system according to the present invention may providethe above-described merge process with a higher priority than thewriting operation of new data when the number of the blank physicalblocks is smaller than the second threshold value. Consequently, thesystem can reduce the rate of the disabled pages to the enabled pages soas to secure the number of the blank physical blocks equal to or greaterthan threshold value. As a result, the system can increase the amountsof data that can be stored.

The second threshold value is smaller than the first threshold valuewhen the above-described flash memory system performs both the operationin the case of the number of the blank physical blocks equal to orsmaller than the first threshold value and the operation in the case ofthe number equal to or smaller than the second threshold value.Consequently, the merge process does not take precedence over thewriting operation of new data until the blank physical blocks are toosmall in number to allow the writing of new data therein. As a result,the extension of the writing duration due to the merge process can bereduced.

The flash memory system according to the present invention may comprisea list of the addresses of the physical blocks and the numbers of thedisabled pages belonging to the physical blocks. The above-mentionedlist is consulted at the time of the selection of the source physicalblock in the above-described merge process. Consequently, the sourcephysical block is selected easily and quickly in decreasing order of thenumber of the disabled areas, the physical block including the largestnumber of the disabled areas first. As a result, the time required forthe above-described merge process decreases since the number of theenabled pages targeted for the above-described merge process isminimized.

The above-described disclosure of the invention in terms of thepresently preferred embodiments is not to be interpreted as limiting.Various alterations and modifications will no doubt become apparent tothose skilled in the art to which the invention pertains, after havingread the disclosure. As a corollary to that, such alterations andmodifications are deemed to fall within the true spirit and scope of theinvention. Furthermore, it is to be understood that the appended claimsare intended to cover any alterations and modifications.

INDUSTRIAL APPLICABILITY

According to the present invention, for flash memories, theper-physical-block ratio of the disabled pages to the enabled pages canbe maintained at a low value. Consequently, a substantial increase inthe storage capacity can be achieved for the flash making the industrialapplicability in the present invention is very high.

1. A flash memory system comprising: (A) a flash memory comprising morethan one physical block including more than one page, each page having(a) a fixed memory capacity and (b) three states, namely, blank,enabled, and disabled states; (B) an address conversion section forconverting a logical address entered from the outside into one of thecorresponding physical addresses of said pages; (C) a read section forreading data from said enabled page; (D) a write section for writingdata onto each of said blank pages; (E) an erase section forcollectively erasing data in each of said physical blocks; (F) apage-disabling section for disabling said enabled pages; and (G) a mergecontrol section for, when said write section writes new data, (a)counting the number of said physical blocks including only said blankpages (which are hereafter referred to as blank physical blocks); (b)selecting a source among said physical blocks in the case of the numberof said blank physical blocks smaller than a first threshold value; (c)selecting, as a source page, said enabled page belonging to said sourcephysical block and substantially as many as said pages on which said newdata is written; (d) copying data on said source page onto said blankpage using said read and write sections; (e) disabling said source pageusing said page-disabling section; (f) selecting said physical blockincluding none of said enabled pages as a erasing target physical block;and (g) performing erasing of data using said erase section for theerasing target physical block, only in the case of said erasing targetphysical block selected.
 2. The flash memory system according to claim1, wherein when said write section writes new data, said merge controlsection: (A) prohibits said write section from writing new data andselects said source physical block in the case of the number of saidblank physical blocks smaller than a second threshold value (here, saidsecond threshold value is smaller that said first threshold value); (B)copies all data on said enabled pages belonging to said source physicalblock onto said blank pages belonging to one of said physical blocksdifferent from said source physical block; and (C) erases data in saidsource physical block using said erase section.
 3. The flash memorysystem according to claim 1 further comprising an address memory forstoring a list of the addresses of said physical blocks and the numbersof said disabled pages belonging to the physical blocks.
 4. The flashmemory system according to claim 1, wherein: (A) a predetermined numberof said pages belonging to each of said separate physical blocks areassigned to one area; (B) said read section reads data in parallel frommore than one of said enabled pages belonging to said same area; (C)said write section writes data in parallel onto more than one of saidblank pages belonging to said same area; and (D) said page-disablingsection disables all of said enabled pages belonging to said same area.5. The flash memory system according to claim 1, wherein: said flashmemory system comprises two or more of said flash memories; and at leasttwo of said read section, said write section, said erase section, saidpage-disabling section, and said merge control section operate inparallel with each other for said respective flash memories.
 6. A methodfor merging data items stored in a flash memory comprising more than onephysical block including more than one page, each page having (a) afixed memory capacity and (b) three states, namely, blank, enabled, anddisabled states, the method when writing new data into said flash memorycomprising the steps of: (A) counting the number of said physical blocksincluding only said blank pages; (B) comparing the count with a firstthreshold value; (C) performing writing of new data and obtaining thenumber of said target pages of the writing in the case of said countsmaller than the first threshold value; (D) selecting a source amongsaid physical blocks; (E) selecting, as a source page, said enabled pagebelonging to said source physical block and substantially as many assaid pages on which said new data is written; (F) copying data of saidsource page onto said blank page; (G) disabling said source page; (H)selecting said physical block including none of said enabled pages as anerasing target physical block; and (I) erasing data in said erasingtarget physical block only in the case of the erasing target physicalblock selected.
 7. The method for merging data items stored in a flashmemory according to claim 6, comprising the further steps of: (A)comparing said count with a second threshold value smaller than saidfirst threshold value; (B) prohibiting writing of said new data in thecase of the count smaller than the second threshold value; (C)selecting, as source pages, all data of said enabled pages belonging tosaid source physical block; (D) copying data of said source page ontosaid blank page belonging to said physical block different from saidsource physical block; and (E) erasing data in said source physicalblock.
 8. The method for merging data items stored in a flash memoryaccording to claim 6, wherein the step of selecting said source physicalblock comprises a substep of consulting a list of addresses of saidphysical blocks and a quantity of said disabled pages belonging to thephysical blocks.